First-in first-out (FIFO) buffers, sometimes called queues, are building blocks for digital systems. Typical implementations include FIFOs built using flip-flops, or on-chip RAM arrays. Ongoing demands for more-complex circuits have led to significant achievements that have been realized through the fabrication of very large-scale integration of circuits on small areas of silicon wafer. These complex circuits are often designed as functionally-defined blocks that operate on a sequence of data and then pass that data on for further processing. This communication from such functionally-defined blocks can be passed in small or large amounts of data between individual integrated circuits (or “chips”), within the same chip, and between more remotely-located communication circuit arrangements and systems. Regardless of the configuration, the communication typically requires closely-controlled interfaces to insure that data integrity is maintained and that chip-set designs are sensitive to practicable limitations in terms of implementation space.
With the increased complexity of circuits, there has been a commensurate demand for increasing the speed at which data is passed between the circuit blocks. Many of these high-speed communication applications can be implemented using parallel data interconnect transmission in which multiple data bits are simultaneously sent across parallel communication paths. Such “parallel bussing” is a well-accepted approach for achieving data transfers at high data rates.
Many integrated circuits today include more than one clock, i.e., frequency, domain; therefore, a data-transmitting module might be operating in one clock domain at a first clock frequency, while a data-receiving module is operating in another clock domain at a different, and perhaps asynchronous, second clock frequency. The interface between clock domains is a clock domain boundary, or clock domain crossing, where information, e.g., data, crosses the boundary.
Implementing integrated circuits using a plurality of clock domains is desirable for a variety of reasons. Accordingly, improving data communication over parallel busses between clock domains, or between modules having different transport and receive rates, permit more practicable and higher-speed parallel bussing applications which, in turn, can directly lead to serving the demands for high-speed circuits while maintaining data integrity.
Even where transmitting and receiving modules reside in the same clock domain, the instantaneous rate at which data are transmitted may not match the instantaneous rate at which data are used (i.e., consumed). To accommodate data rate differences, a discrete buffering device is conventionally used between different clock domains, or between components having different transmit and receive rates. Data is clocked, i.e., inserted, into the buffering device according to a source domain or write clock, and clocked out, i.e., extracted, from the buffering device according to a receive domain or read clock.